As integrated circuits are produced with greater and greater levels of circuit density, efficient testing schemes that guarantee high fault coverage while minimizing test costs and chip area overhead have become essential. The number of transistors that can be placed on a chip has been doubling roughly every eighteen months, as predicted by Moore's law. The amount of data required to test such massively complex chips has been increasing even more rapidly. In practical terms, for very large integrated circuits, the test cost is approaching (and may even exceed) the design cost. To address the rapid increase in volume of test data, a number of compression schemes have been developed.
Many integrated circuits are tested using structured design-for-testability (“DFT”) techniques, which employ the general concept of making some or all state variables (for example, memory elements, such as flip-flops and latches) directly controllable and observable. Preferably, a circuit is treated, as far as testing of combinational faults is concerned, as a combinational or a nearly combinational network. The most-often used DFT methodology assumes that during testing all (or almost all) memory elements are connected into one or more shift registers termed “scan chains.” See, for example, U.S. Pat. No. 4,503,537.
A circuit that utilizes scan chains for testing typically has two basic modes of operation: a normal mode and a test (or scan) mode. In the normal mode, the memory elements perform their regular functions. In the scan mode, the memory elements become scan cells that are connected to form a number of scan chains. These scan chains are used to shift test patterns into the circuit and to shift out circuit responses to the test patterns (referred to as “test responses”). The test responses can then be compared to fault-free responses to determine if the circuit-under-test (“CUT”) works properly.
Scan design methodology has gained widespread adoption by virtue of its simple automatic test pattern generation (“ATPG”) and silicon debugging capabilities. Today, ATPG software tools are so efficient that it is possible to generate test sets (a collection of test patterns and expected test responses) that guarantee almost complete fault coverage of several types of fault models including stuck-at and transition faults. It is also possible to target other fault models, such as path delay and bridging faults. As part of ATPG, unknown states (sometimes referred to as “X” states or “unknowns”) in the test responses that are created upon application of one or more of the test patterns to the circuit-under-test are identified. Thus, the expected test responses may contain one or more unknown values. Unknown values typically result from limitations of simulation technology that cannot accurately predict the logic values of certain signals in a circuit during simulation. Because the actual logic values that these signals will assume in a manufactured circuit cannot be determined during simulation, the signals are designated as unknowns.
One type of scan design methodology that has gained widespread adoption is termed “full scan” and does not utilize any type of decompression or compression technique to reduce the size of the test data being sent and received by the external test hardware. Although full scan enables high test quality, the cost of full scan testing has become prohibitive because the number of scan cells in designs is increasing while the number of chip test pins and tester channels that can be used for scanning in and scanning out are limited. To compensate for this limitation, longer scan chains are typically used, implying larger test data volumes and longer chain load-unload times.
To overcome these issues, several test data compression techniques can be used that involve breaking long scan chains into a large number of shorter chains. To access the shorter chains using a relatively small number of test pins, test data decompression hardware (referred to herein as a “decompressor”) is typically used on the input side of the CUT. Similarly, to reduce the number of test output pins, a test response compactor is used on the output side of the CUT to receive the test responses and to compact the responses, thereby producing “compacted test responses.”
FIG. 1 shows an example of such a configuration. In particular, FIG. 1 is a block diagram of a system 100 for testing digital circuits with scan chains and compression hardware. During a typical scan mode, external automated test equipment (“ATE”) or tester 102 applies a set of compressed test patterns 104 to a CUT 106 via input test pins 114. The compressed test patterns are input into a decompressor 110, which decompresses the compressed test patterns into the test patterns that are applied to the scan chains 108 within the CUT 106. Typically, the test patterns comprise a number of deterministically specified bits targeting one or more defects, and thus are termed “deterministic test patterns.” Examples of compactors as may be used in the system 100 are described, for instance, in J. Rajski et al., “Embedded deterministic test for low cost manufacturing,” Proc. IEEE International Test Conference, pp. 301-310 (2002). Once the scan chains 108 have been loaded with a decompressed test pattern, the CUT 106 is run in normal mode using the test patterns for input values. The CUT 106 may be run for a designated period of time (for example, one clock cycle) after which the circuit response to the test pattern (the test response) is captured and stored in the scan chains 108. With the circuit again in scan mode, the test response is clocked out of the scan chains 108 and into the compactor 112. The compactor 112 produces a compacted version of the test responses (in space, time, or both space and time), which is routed back to the tester 102 through output test pins 116. The tester 102 compares the compacted test responses 118 to expected, fault-free, versions 120 of the compacted test responses. From this comparison, a determination can be made as to whether the CUT 106 is operating as expected (for example, producing a “go” signal at node 122), or is not operating as expected (for example, producing a “no go” signal at the node 122).
Currently available test response compaction schemes can be grouped into three classes: (1) infinite input response compaction schemes (also known as “time compactors”); (2) finite memory compaction schemes; and (3) space compaction schemes (also known as “spatial compactors,” “linear compactors,” or “space compactors”).
Time compactors typically have a feedback structure with memory elements for storing a signature, which represents the results of the test. After the signature is completed, it is read and compared to a fault-free signature to determine if an error exists in the circuit-under-test. Time compactors, for example, may use polynomial division, counting-based techniques, and check-sum-based methods, and are typically employed in built-in self-test (BIST) applications. The actual compaction is usually performed by linear finite state machines, such as a linear feedback shift register (“LFSR”), a MISR, or cellular automata. In general, time compactors cannot handle unknown states in a test response. For example, because these systems include feedback, an unknown state will circulate in the compactor endlessly until the compactor is reset. Thus, all states can become unknown after a few cycles, thereby corrupting the test signature and rendering the test useless.
Finite memory compactors are compactors that have memory but produce a finite response to a test response vector. Thus, for example, test response values that are input into the compactor can be clocked completely out of the compactor after a finite period of clock cycles and before an entire test response is loaded or an entire signature is output. Examples of such compactors are described in further detail in U.S. Published Patent Application No. 2004/0230884 entitled “Compressing Test Responses Using a Compactor,” which is hereby incorporated herein by reference.
Space (or spatial) compactors comprise combinational circuits that are often predominantly built from XOR (or XNOR) networks and do not typically contain memory elements or any feedback structure. (Note, however, that a space compactor with memory elements inserted for pipelining purposes is still considered to be a space compactor). Spatial compaction networks are generally configured to generate m compacted test outputs from n scan chain outputs of the CUT, where m<n.
Space compactors typically offer smaller compaction ratios than time compactors, but are generally better suited to handle unknown states in a test response. For example, some spatial compaction schemes use coding theory to guide the design and implementation of the compactor. Such compactors are referred to generally as compactors using error correcting codes (ECC) or ECC-based compactors. However, in order to use ECC-based compactors in the presence of unknown values and to still detect an error, enhanced ATE support is usually needed (for example, for each scan out cycle, one might need to compare the compacted response to several different possible correct responses). This is not easily done in a conventional scan test environment. Alternatively, proper error detection may require post-processing, off-chip analysis of test responses in order to determine if they passed or failed. This can be problematic in “go/no-go” production testing, and can also increase the test time because storing test responses on a tester is slower than just comparing responses on chip pins.
In order to address these issues, one can expend more on chip as well as in tester data resources. One way to do this is to use specialized codes for designing the compactor that segregate the unknowns from the error information in the compacted response. However, creating such specialized codes can be extremely difficult, especially for multiple unknowns. In one known approach, referred to herein as the X-Compactor approach, for example, special codes to handle only a single unknown are presented. See Mitra, S., et al., “X-Compact: An Efficient Response Compaction Technique, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol, 23, no. 3 (March 2004). Creating codes for handling more than one unknown requires solving an NP-complete problem. Moreover, approaches using these specialized codes, such as the X-Compactor approach, require many more output pins than other compactors using ECC. Consequently, the output response data storage requirement and the memory requirements on the ATE are significantly increased. The use of additional output pins to handle unknowns can be undesirable because only a fraction of the shift cycles ordinarily contain unknown values.
Another way to achieve the above objective is to mask the output response bits that are unknowns before compaction. This method typically does not increase the number of output pins, but requires additional input pins to pass the information concerning the location of the unknowns (“X” values) in the test response to the masking hardware. So, in order to mask up to x unknowns, the masking logic will require xlogn inputs (where n is the number of bits in the uncompacted test response). Once the unknown values are masked, the test response can be compacted using “off-the-shelf” error correcting codes. Because masking is done before the test response is compacted, however, this approach requires O(nx) additional hardware.